1. Field of the Invention
The present invention generally relates to an apparatus and method for constructing a memory cell using capacitors as load elements. The capacitor loaded memory cell of the present invention operates as a static random access memory (SRAM) cell when a particular capacitor/transistor connection is chosen.
2. Description of Related Art
As is well known in the art, there are basically two types of metal oxide semiconductor (MOS) random access memories (RAMS): static and dynamic. A static RAM or SRAM is a form of semiconductor memory based on the logic circuit known as a flip-flop, which retains information as long as there is enough power to operate the device. These flip-flops have to be simple in order to minimize the silicon area per cell, which is very important since the cell array constitutes by far the largest part of the memory chip. The problem with standard SRAMS is their large size, owing to the use of six transistors in each memory cell where all six are aligned in one plane of the silicon wafer containing them.
Dynamic RAMS (DRAMS) on the other hand store binary data on capacitors resulting in a further reduction in a cell area at the expense of a more elaborate read/write circuitry. The binary data stored in DRAMs is in the form of the charge on the capacitor.
Due to various leakage effects (i.e., current drain) that are inevitably present, the capacitor charge will eventually leak off. Thus, to insure proper operation of DRAMs, a refresh operation must be completed periodically. During the refresh operation, the memory cells' content is read and the data stored therein is rewritten, thus restoring the capacitor charge to its proper value. The refresh operation must be performed every few milliseconds (eg. eight to sixteen milliseconds) and thus implies the necessity of having a clock connection to the DRAM circuit. This periodic refresh operation required in the DRAMs operation requires that additional refresh circuitry must be included in the design thereby increasing the surface area of the circuit.
Nevertheless, since the DRAM memory cell has such few components and the DRAM cells are smaller, the DRAMs achieve greater packing density than is possible with any static RAM. Despite being slower, DRAMs are more commonly used than SRAMs because of the smaller DRAM cell design that allows a DRAM to hold up to four times as much data as a SRAM within the same surface area on the integrated circuit.
Heretofore, SRAMs and DRAMs have not fulfilled the desiderate of providing a memory cell with materially reduced circuit complexity and a high speed of access.